1. Field of The Invention
The invention relates to the field of semiconductor manufacture, in particular, the manufacture of arrays of integrated silicon-germanium heterobipolar transistors.
2. Background Information
In addition to gallium-arsenide transistors, silicon-germanium heterobipolar transistors (SiGe HBTs) are increasingly being used for applications in the extremely high frequency range (for example in communications technology or in satellite circuits). Integrated NPN transistors with the layer sequence N-Si collector layer, P-SiGe base layer, N-Si emitter layer and N.sup.+ -Si emitter connection layer are preferably used, where the thin SiGe base layer (layer thickness approx. 30-80 nm)--strained due to the differing lattice constants of silicon and silicon-germanium (SiGe)--is of crucial importance for the operation and the properties of the transistor.
The semiconductor array of the SiGe HBTs is preferably made using epitaxy methods (gas phase epitaxy/CVD, molecular beam epitaxy/MBE) or by implantation methods. Problems occur during the manufacturing process in particular because
the process temperature must not exceed certain values (typically 700.degree. C.) in order to prevent any relaxation of the strained SiGe layer, PA1 every interruption in the growth of the layer structure (collector, base, emitter, emitter contact) on the one hand necessitates a high-temperature cleaning operation (risk of relaxation of the SiGe layer) and on the other hand contaminates the sensitive emitter/base boundary surface or base/collector boundary surface now exposed, i.e. not covered. PA1 doping of the semiconductor layers after manufacture of the layer structure poses difficulties: firstly, the requirement that the Si/SiGe boundary surfaces on the one hand and the PN junctions on the other hand are exactly congruent in order to avoid disadvantageous component properties is difficult if not impossible to achieve; secondly, intolerable damage occurs when implanting the dopants in the semiconductor layers, and necessitates an additional anneal process step, which in its turn causes unwelcome diffusion processes, PA1 in order to form contacts, the deposited semiconductor layers have to be partially removed again; this results in the formation of unpassivated Si or SiGe surfaces that cause leakage currents. Subsequent passivation of these surfaces can only be achieved with difficulty and the leakage currents cannot be completely suppressed. PA1 a) the manufacture of the complete layer structure of the HBT--the layer growth (collector layer, base layer, emitter layer, emitter contact layer) including doping of the layers--is implemented in a single, uninterrupted process (for example by MBE or CVD); this rules out any contamination between the critical transistor layers. During layer growth, a high-temperature cleaning operation is not necessary, so that the strained SiGe layer cannot relax; since no subsequent doping of the semiconductor layers is necessary, the problems entailed by diffusion processes or implantation processes are not encountered. PA1 b) a base connection region is formed and a double-mesa structure of the semiconductor array is formed such that the two PN junctions in the area of the base connection region (base/emitter/PN junction and base/collector/PN junction) are respectively above and below the SiGe layer (base/emitter boundary layer or base/collector boundary layer). To this purpose, part of the emitter contact layer is first removed in a etching step using an auxiliary layer--however the SiGe layer remains "buried" underneath the Si emitter layer, so that there is no silicon/germanium at the surface. Then an implantation process is carried out (for example self-aligned by means of a first spacer oxide layer), whereby on the one hand the exposed emitter layer is redoped (changed into a base connection region) and on the other hand the external base/collector/PN junction is slightly moved into the Si layer underneath the SiGe layer or underneath the base/collector boundary layer. Self-alignment firstly allows the distance from the base connection region to the emitter contact layer to be kept small (minimal), so that the extrinsic base resistance, too, is minimized (which is also advantageous for good HF properties of the component); secondly, the points at which the PN junctions break the surface are in the silicon layer and are not in contact with the silicon-germanium. Finally, part of the base connection region and of the collector layer is selectively removed in order to form a mesa-type structure by a second (mesa) etching step with the aid of a mask; furthermore, field oxide regions for separation of the active structures of the integrated circuit are formed. PA1 c) by thermal oxidation over the entire exposed surface of the semiconductor array, a high-quality silicon dioxide layer is formed, such that the PN junctions on the surface, which are not in contact with the silicon-germanium layer, are very effectively protected (passivated) and only slight leakage currents occur. PA1 d) the base connection contact is brought as close as possible to the inner base zone by a second self-aligned process step. With the aid of a second spacer oxide layer--which is wider than that in the first self-aligned process step--this distance is self-aligned and minimized. PA1 the drawbacks described at the outset are avoided during the manufacturing process, PA1 the semiconductor array is manufactured with self-alignment by the use of spacers, PA1 the dimensions of the component can be reduced, PA1 the component retains its favorable (high frequency) properties in an integrated circuit, too.